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Esperanto Technologies Engineers to Present at RISC-V Workshop Barcelona(May 03, 2018)
Presentations on Security, Vector Extensions, Privileged Instruction Set Architecture
MOUNTAIN VIEW, Calif., May 03, 2018 (GLOBE NEWSWIRE) -- Esperanto Technologies™, a developer of high-performance, energy-efficient computing solutions based on RISC-V for artificial intelligence and machine learning applications, will participate in the RISC-V Workshop Barcelona, May 7-10. Esperanto is a Founding, Gold member of the RISC-V Foundation.
Co-hosted by the Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC) and sponsored by NXP and Western Digital in Barcelona, Spain, this upcoming RISC-V Workshop will feature recent technical activity in the ever-expanding RISC-V ecosystem. View the agenda here.
The RISC-V Workshop Barcelona 2018 will feature an Esperanto exhibit and several presentations by Esperanto.
Exhibit: Esperanto will feature technology demonstrations related to their initial System-on-Chip (SoC) plans, based on the 64-bit free and open RISC-V Instruction Set Architecture (ISA), including:
- Artificial intelligence (AI) supercomputer-on-a-chip designed with leading edge 7nm CMOS
- ET-Maxion™ 64-bit RISC-V cores for highest single thread performance
- Thousands of ET-Minion™ energy-efficient RISC-V cores each with a vector floating point unit
Workshop Presentation: “Securing High-performance RISC-V Processors from Time Speculation.” Christopher Celio and Jose Renau, CPU Architects from Esperanto Technologies, will discuss potential changes to future high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown. They will present a proposal for RISC-V cores which minimizes changes to the RISC-V ISA or platform specifications in order to provide security against timing-based attacks. These proposals are being previewed with the RISC-V community to solicit comments prior to implementation in RISC-V chips. The presentation is Wednesday, May 9 at 1:15 pm Barcelona time. See https://tmt.knect365.com/risc-v-workshop-barcelona/agenda/3#workshop_securing-high-performance-risc-v-processors-from-time-speculation
Tutorial Presentations: “Vector ISA.” Roger Espasa, Chief Architect at Esperanto Technologies, will deliver a tutorial on basic semantics and operation of the vector extension, including new states, configuration, instruction encoding and inter-operation, and more, on Monday, May 7 at 3:20 pm Barcelona time. See https://tmt.knect365.com/risc-v-workshop-barcelona/agenda/1#tutorials_vector-isa
Workshop Presentation: “Vector ISA Proposal Update.” Espasa will present a summary of the latest updates to the Vector ISA specification for the wider audience on Tuesday, May 8 at 10:00 am Barcelona time. See https://tmt.knect365.com/risc-v-workshop-barcelona/agenda/2#workshop_vector-isa-proposal-update
Tutorial Presentation: Privileged ISA. Allen Baum, CPU Architect at Esperanto Technologies, will present a tutorial on the RISC-V privileged ISA, including a discussion on privileged architecture needs, features, modes and use case profiles. The presentation is on Monday, May 7 at 1:50 pm Barcelona time. See https://tmt.knect365.com/risc-v-workshop-barcelona/agenda/1#tutorials_privileged-isa
Esperanto president and CEO Dave Ditzel commented, “Esperanto is proud to be a founding member of the RISC-V Foundation, and a key contributor to the ongoing programs they have sponsored worldwide. Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications, driving computing innovation for the next decade.”
"Esperanto is very active in the RISC-V ecosystem and in several mission-critical technical working groups and committees," said Rick O’Connor, executive director of the non-profit RISC-V Foundation. "Esperanto exemplifies how members of the RISC-V community are working together to accelerate the wide adoption of the RISC-V architecture, and for expanding our partner and developer ecosystem."
Please contact [email protected] to set up a meeting with Esperanto at the RISC-V Workshop Barcelona, or to learn more about Esperanto Technologies. “Join the RISC-V Revolution!” a disruptive force transforming the microprocessor market through collaboration on open standards.
About the RISC-V Workshop Barcelona
- Where: Universitat Politècnica de Catalunya, in Barcelona, Spain.
- When: May 7 - 10, 2018.
- More information: Click here for RISC-V Workshop Barcelona.
About Esperanto Technologies
Esperanto Technologies develops high-performance, energy-efficient computing solutions based on the open standard RISC-V ISA. Esperanto is headquartered in Mountain View, California with engineering sites in the United States, European Union, and Eastern Europe. Esperanto has brought together a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications such as Machine Learning. For more information, please visit https://www.esperanto.ai/
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